1. Field of the Invention
The present invention generally relates to computer systems, and more particularly to a system for performing high-speed data transfers from a computer system memory to an ATM (asynchronous transfer mode) card, via a cache memory.
2. Discussion of the Related Art
In computer system design, a principal objective is to continually design faster and more efficient computer systems. In this regard, most conventional high-performance computer systems include cache memories. As is known, a cache memory is a high-speed memory that is positioned between a microprocessor and main memory in a computer system in order to improve system performance. Typically, cache memories (or caches) store copies of portions of main memory data that are actively being used by the central processing unit (CPU) while a program is running. Since the access time of a cache can be faster than that of main memory, the overall access time can be reduced.
Even though cache memories typically increase system performance, further improvements are desired. For example, consider a computer system having separate busses, such as a system bus that interconnects a central processing unit (e.g., a microprocessor), memory, etc., and an I/O bus (e.g., ISA bus, PCI bus, etc). One of the bottlenecks that has limited the performance of personal computers in the past has been the maximum specified speed of the I/O bus. In original IBM PC AT computers manufactured by IBM Corp., the I/O bus operated with a data rate of 8 MHz (BCLK=8 MHz). This was an appropriate data rate at that time since it was approximately equivalent to the highest data rates which the CPUs of that era could operate with on the host bus. CPU data rates are many times faster today, however, so the slow speed of the I/O bus severely limits the throughput of systems today. One solution for this problem has been the development of local bus standards, by which certain devices which were traditionally located on the I/O bus can now be located on the host bus--e.g., the VESA VL-Bus Local Bus Standard.
Another solution to the problem has been the development of another standard, referred to herein as the PCI standard. The PCI bus achieves very high performance, in part because its basic data transfer mode is by burst. That is, data is always transferred to or from a PCI device in a known sequence of data units defined by a known sequence of data unit addresses in an address space. In a "cache line" burst mode, a predetermined number of transfers take place. In a "linear" burst mode, any number of transfers (including 1) can take place to/from linearly sequential addresses until either the initiator or the target terminates the transaction. In either mode, the initiator need only specify the starting address because both parties know the sequence of addresses which follow.
The implementation of the PCI bus is well known in the industry and its specifications are available to the public. In transferring data to and from a high speed industry standard common bus, often it is desirable to provide an intermediate local cache buffer for the data to allow the bus to maintain full bandwidth. That is, it is desirable to maintain full utilization of the I/O bus that interfaces the PCI bus to the cache, without overtaxing the system bus. For example, when data is fetched from memory to the cache, it is fetched one cache line at a time.
When data is first requested by a device on the PCI bus, there is an initial latency period (idle I/O clock cycles) while the first cache line of data is retrieved from memory to the cache. If the PCI transfer requires more than one cache line of data, then another latency period is encountered while the next cache line of data is retrieved from system memory to the cache. Intermittent latency periods are encountered each time a new line of data is read from memory to the cache. It would therefore be desirable to eliminate or significantly reduce these latency periods. One way of achieving this goal is to always pre-fetch an additional cache line of data. For example, initially two cache lines of data could be retrieved from memory to the cache. After the first line of data has been transferred from the cache to the PCI bus and the second line is being transferred to the PCI bus, then an additional cache line of data could be fetched from memory into the cache.
While this approach would reduce the idle cycles encountered on the I/O bus, it realizes an inefficient utilization of system resources. The problem with this approach is that it over-fetches data from memory into the cache (by one cache line). Therefore, it unnecessarily consumes bandwidth of the system bus. In addition, it wastes a portion of the cache memory. Such poor utilization of the cache memory space denigrates overall system performance.
Accordingly, there is a desire to provide an improved system and method for interfacing a cache to a PCI bus that overcomes the above-identified and other shortcomings.